D type flip flops
Introduction
A flip-flop (sometimes called a 'latch') in logic gate diagrams is a design that can be used to store a single bit of information, either a one or a zero. You can flip over this stored information (from 1 to 0 or from 0 to 1) by applying an input signal and flip back again by applying another input signal but the output only ever changes if there is a rising clock edge - we will discuss what that means in much more detail below. It cannot change at other times in a clock cycle. This is where the design gets its name from. It is a fundamental component in the design of anything digital, such as computers and digital communications. There are a number of different flip-flop designs but the only one on the OCR syllabus is the D type flip-flop.
The D type flip-flop has 2 inputs and 2 outputs. We can represent one using this logic symbol:
The first input is the data signal, which we use when we want to change the output Q. The second input is the signal from a clock. You can think of the clock as a never-ending series of digital pulses that look like this:
Each pulse of the clock has a rising edge:
and a falling edge:
There are two outputs. We will call it Q and it is either a 0 or a 1. We will call the other output Q-bar and we usually represent it as a Q with a bar over it. It always holds the opposite value to whatever is in Q.
How does the D flip-flop work?
The first thing to know is that the output Q always takes on whatever state the Data signal D is in, but only when the clock is on a rising edge. So if the input data signal is a 0 and the clock is on a rising edge, then Q is 0. If the input data signal is a 1 and the clock is on a rising edge, then Q is 1. This is where the flip-flop gets its name from; the output Q takes its value from the input D and then it delays it for one clock cycle, until the next rising edge. At any other time in the clock cycle, the value of Q holds whatever value it previously had. If that sounds complicated, then a truth table might help!
Even the truth table can be a little bit confusing. If we look at what is called a 'timing diagram', we might be able to see exactly how this functions.
As you can see, the output Q starts off at 0. At X1, the clock is on a rising edge and because the Data is a 1, Q becomes 1. It stays at a 1 until X2, when it changes to a 0 because the clock is on a rising edge and the Data signal is a 0. At X3, Q becomes a 1 because there is a rising edge and the data signal is a 1. Note that we haven't shown what Q-bar is. If you remember from our earlier description, it is the exact opposite of whatever Q is! We can implement the D type flip-flop using 4 NAND gates and a NOT gate, like this:
